1. Field of the Invention
The present invention relates to interfaces for CCD register systems and in particular to interface circuitry for allowing for a PARTIAL-WRITE operation on a CCD storage register.
2. Description of the Prior Art
In order to effectively utilize CCD technology, high density must be obtained. The smallest possible cell sites for storage of charge is desirable as well as an optimum spacial configuration of cell sites within a register in order to achieve high density. In practical applications of CCDs, the density problem is present not only at this configurational level, but also with respect to circuitry required for interfacing between registers and the rest of the data processing system. This communication takes place via data buses or possibly via a single bi-directional data bus. Obviously, in the latter case, less space is required and higher system density is possible. Similarly, if circuits for controlling the input and output of signals to these registers are designed to occupy a minimum amount of space, then higher densities will result.
High-density CCD storage registers are described in Related Applications Nos. 1 and 2. They have the capacity for storing a high number of bits, 256, in a relatively small amount of space. During any cycle of operation (i.e. READ, WRITE or REFRESH), all 256 bits are transferred into the register. However, during WRITE cycles, it is often a wasteful operation to bus all 256 bits from the rest of the system, since it is often required to WRITE (store) less than 256 bits. Typically, blank bits are written during each cycle. If interface circuitry can be provided which allows for a PARTIAL-WRITE mode operation, then system efficiencies would result. Specifically, a PARTIAL-WRITE in this context denotes utilization of other (other than the CCD register system) system components for only that period of time (or for that number of bits) required for transmission of bits of present interest. After such a PARTIAL-WRITE is completed, the other system components are no longer dedicated to performance of the transmission task and may be assigned to performance of other tasks. In this manner, overall system efficiency is increased. In other words, if interface circuitry can be provided for enabling a PARTIAL-WRITE operation, efficiencies in other parts of the data processing system are possible. Unfortunately, with respect to CCD technology, prior art PARTIAL-WRITE circuitry has been either complex and/or space consuming. This is in direct contrast with the CCD requirement of high density and cost savings.